This invention relates to semiconductor devices, and more particularly to memory devices of the dynamic read/write type having a nibble mode of operation.
One of the types of data input/output for a random access read/write memory is the so-called "nibble mode", in which data in addressed in four-bit "nibbles" and the four bits are then read or written sequentially through single-bit data terminals. Semiconductor dynamic MOS RAMs of the 64K, 256K or 1-Megabit size may be constructed in this manner, for example. A dynamic RAM circuit particularly suitable for this mode of operation is disclosed in U.S. Pat. No. 4,239,993, where four sets of I/O lines are brought out from the cell array in parallel, so four bits are accessed at one time. However, the starting address for the first bit does not necessarily fall on the same boundaries as those used for the array I/O lines. The nibble mode circuitry must allow the starting address to by any column, not just every fourth column. Previous methods of accomplishing this have been slow in nibble access time.
It is the principal object of this invention to provide improved high-speed input/output circuitry for semiconductor memory devices, particularly for "nibble mode" operation. Another object is to provide improved nibble mode circuitry for DRAMs which permits fast access beginning at any column address.